The present invention relates generally to metal-oxide-semiconductor (MOS) devices, and more particularly relates to techniques for improving the high-frequency performance of an MOS device.
Power MOS devices, including lateral diffused MOS (LDMOS) devices, are employed in a variety of applications, such as, for example, power amplifiers in wireless communications systems. In applications where high-frequency operation is desired, such as in a radio frequency (RF) range (e.g., above 1 gigahertz (GHz)), a conventional LDMOS device generally uses a shorter gate length, in comparison to the gate length of a typical LDMOS device that is not adapted for high frequency applications, in order to improve the RF performance of the device. However, reducing the gate length undesirably increases hot-carrier degradation in the device. Moreover, reducing the gate length also increases the gate resistance (Rg) associated with the device. Since the output gain of the MOS device is inversely proportional to the gate resistance of the device, increasing the gate resistance results in a decrease in the output gain of the device, which is particularly undesirable in an amplifier application.
It is well known that the transconductance associated with an MOS device may be increased by proportionally decreasing the thickness of a gate oxide layer in the device. However, using a thinner gate oxide undesirably results in a higher gate-to-source capacitance (Cgs), which may undesirably effect high frequency performance of the device. It would be desirable to reduce the gate oxide thickness in a given MOS device without significantly increasing the gate-to-source capacitance associated with the device.
Hot-carrier degradation (HCD) in an MOS device generally results from heating and subsequent injection of carriers into the gate oxide of the device, which results in a localized and nonuniform buildup of interface states and oxide charges near and underneath a gate of the device. This phenomenon can produce undesirable variations in certain characteristics of the MOS device, including threshold voltage, transconductance, drain current, etc., thus impacting the operation and reliability of the device. It is well known that HCD is a strong function of the internal electric field distributions of the MOS device.
While the lateral electric field near the gate in a drain side of the device is primarily responsible for heating and avalanche, the transverse electric field primarily influences carrier injection into the gate oxide. The reduction of channel length in the MOS device affects the internal electric field distributions, and hence the carrier heating and injection processes. As device geometries shrink, the localized internal electric field distributions can become even higher in the device, thus exacerbating the problem.
Accordingly, it would be advantageous to have an MOS device capable of improved high frequency performance, such as power gain and efficiency, without increasing hot-carrier degradation in the device.
The present invention provides techniques for improving high frequency performance of an MOS device without significantly impacting the hot-carrier degradation characteristics of the device. Moreover, the techniques of the present invention can be used to fabricate an integrated circuit (IC) device, for example, an LDMOS device, using conventional complementary metal-oxide-semiconductor (CMOS) compatible process technology. Consequently, the cost of manufacturing the IC device is not significantly increased. Furthermore, the techniques of the present invention may be used to form an MOS device which is easily integrated with standard CMOS circuits for achieving improved high frequency and/or high power performance.
In accordance with one aspect of the invention, an MOS device is formed comprising a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. The MOS device further comprises a first gate formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions, the first gate comprising a plurality of sections spaced apart from one another, and a second gate formed proximate the upper surface of the semiconductor layer, the second gate comprising a first end formed between at least two of the plurality of sections of the first gate and a second end opposite the first end formed above at least a portion of the first gate, the second end being wider than the first end, the first and second gates being electrically isolated from one another. The device may be configured such that a channel is formed between the first and second source/drain regions in response to a first signal in a first frequency range, which may be a direct current (DC) bias voltage applied to the first gate, and to at least partially modulate the channel in response to a second signal in a second frequency range applied to the second gate.
These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.